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@article{Joosten13a,
Abstract = {Even though the ACL2 logic is first order, the ACL2 system offers several mechanisms providing users with some operations akin to higher order logic ones. In this paper, we propose a macro, named instance-of-defspec, to ease the reuse of abstract functions and facts proven about them. Defspec is an ACL2 book allowing users to define constrained functions and their associated properties. It contains macros facilitating the definition of such abstract specifications and instances thereof. Currently, lemmas and theorems derived from these abstract functions are not automatically instantiated. This is exactly the purpose of our new macro. instance-of-defspec will not only instantiate functions and theorems within a specification but also many more functions and theorems built on top of the specification. As a working example, we describe various fold functions over monoids, which we gradually built from arbitrary functions.},
Author = {Joosten, Sebastiaan Jozef Christiaan and van Gastel, Bernard and Schmaltz, Julien},
Journal = {arXiv preprint arXiv:1304.7875},
Title = {A macro for reusing abstract functions and theorems},
Year = {2013},
Month = {4},
Day = {30},
Note = {This paper was presented at the ACL2 Workshop 2013},
Local-Url = {ACL22013Macro.pdf}
}
@inproceedings{Verbeek13,
Abstract = {Scalable formal verification constitutes an important challenge for the design of complicated asynchronous circuits. Deadlock freedom is a property that is desired but hard to verify. It is an emergent property that has to be verified monolithically. We propose to use Click, an existing library of asynchronous primitives, for verification. We present the automatic extraction of abstract SAT/SMT instances from circuits consisting of Click primitives. A theory is proven that opens the possibility of applying existing deadlock verification techniques for synchronous communication fabrics to asynchronous circuits.},
Author = {Verbeek, Freek and Joosten, Sebastiaan Jozef Christiaan and Schmaltz, Julien},
Booktitle = {Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on},
Organization = {IEEE},
Pages = {183--190},
Title = {Formal deadlock verification for click circuits},
Year = {2013},
Month = {May},
DOI = {10.1109/ASYNC.2013.21},
Local-Url = {ASYNC2013Click.pdf}
}
@inproceedings{Joosten13,
Abstract = {Communication fabrics constitute a key component of multicore processors and systems-on-chip. To ensure correctness of communication fabrics, formal methods such as model checking are essential. Due to the large number of buffers and the distributed character of control, applying these methods is challenging. Recent advancements in the verification of communication fabrics have demonstrated that the use of inductive invariants provides promising results towards scalable verification of Register Transfer Level (RTL) designs. In particular, these invariants are key in the verification of progress properties. Such invariants are difficult to infer. So far, they were either manually or automatically derived from a high-level description of the design. Important limitations of these approaches are the need for the high-level model and the necessary match between the model and the RTL design. We propose an algorithm to automatically derive these invariants directly from the RTL design. We consider communication fabrics to be a set of message storing elements (e.g, buffers) and some routing logic in-between. The only input required by our method is a definition of when messages enter or leave a buffer. We then exploit this well-defined buffer interface to automatically derive invariants about the number of packets stored in buffers. For several previously published examples, we automatically generate the exact same invariants that were either manually or automatically derived from a high-level model. Experimental results show that the time needed to generate invariants is a few seconds even for large examples.},
Author = {Joosten, Sebastiaan Jozef Christiaan and Schmaltz, Julien},
Booktitle = {Formal Methods and Models for Codesign (MEMOCODE), 2013 Eleventh IEEE/ACM International Conference on},
Organization = {IEEE},
Pages = {57--64},
Title = {Generation of inductive invariants from register transfer level designs of communication fabrics},
Year = {2013},
Month = {Oct},
Day = {18},
Slides = {SlidesJoosten13.pdf},
Local-Url = {MEMOCODE2013Generation.pdf}}
@article{Joosten13b,
Abstract = {The 3-partition problem admits a straightforward formulation as a 0-1 Integer Linear Program (ILP). We investigate problem instances for which the half-integer relaxation of the ILP is feasible, while the ILP is not. We prove that this only occurs on a set of at least 18 elements, and in case of 18 elements such an instance always contains an element of weight ≥ 10. These bounds are sharp: we give all 14 instances consisting of 18 elements all having weight ≤ 10. Our approach is based on analyzing an underlying graph structure.},
Author = {Joosten, Sebastiaan Jozef Christiaan and Zantema, Hans},
Pdf = {CTW2013Relaxation},
Publisher = {Enschede: University of Twente},
Title = {Relaxation of 3-partition instances},
Year = {2013},
Month = {May},
Day = {21},
Local-Url = {CTW2013Relaxation.pdf},
Slides = {SlidesJoosten13b.pdf}}
@mastersthesis{Joosten11,
Author = {Joosten, Sebastiaan Jozef Christiaan},
Date-Modified = {2018-08-07 16:34:25 +0200},
Local-Url = {MSc2011Relaxations.pdf},
School = {University of Twente},
Title = {Relaxations of the 3-partition problem},
Year = {2011},
Month = {Dec},
Day = {21},
Slides = {SlidesMScPresentatie.pdf},
Note = {[Slides in English](/publications/SlidesMScPresentation.pdf)}
}
@inproceedings{Michels11,
Abstract = {Relation algebra can be used to specify information systems and business processes. It was used in practice in two large IT projects in the Dutch government. But which are the features that make relation algebra practical? This paper discusses these features and motivates them from an information system designer's point of view. The resulting language, Ampersand, is a syntactically sugared version of relation algebra. It is a typed language, which is supported by a compiler. The design approach, also called Ampersand, uses software tools that compile Ampersand scripts into functional specifications. This makes Ampersand interesting as an application of relation algebra in the industrial practice. The purpose of this paper is to define Ampersand and motivate its features from a practical perspective. This work is part of the research programme of the Information Systems & Business Processes (IS&BP) department of the Open University.},
Author = {Michels, Gerard and Joosten, Sebastiaan Jozef Christiaan and van der Woude, Jaap and Joosten, Stef},
Booktitle = {International Conference on Relational and Algebraic Methods in Computer Science},
editor = "{Swart, de}, H.",
Organization = {Springer, Berlin, Heidelberg},
Pages = {280--293},
Title = {Ampersand: Applying Relation Algebra in Practice},
Year = {2011},
Month = {May},
DOI = {10.1007/978-3-642-21070-9_21},
Local-Url = {RAMICS2011Ampersand.pdf}}
@article{Joosten07,
Author = {Joosten, Stef M M and Joosten, H. J M and Joosten, Sebastiaan Jozef Christiaan},
Journal = {Informatie, juli/augustus, 42-50},
Title = {Ampersand: foutvrije specificaties voor B\&I vraagstukken},
Year = {2007},
Month = {Jul},
Local-Url = {Informatie2007Ampersand.pdf}}
@inproceedings{Joosten14a,
Abstract = {In the realm of multi-core processors and systems-on-chip, communication fabrics constitute a key element. A large number of queues and distributed control are two important aspects of this class of designs. These aspects make decomposition and abstraction techniques difficult to apply. For this class of designs, the application of formal methods is a real challenge. In particular, the verification of liveness properties is often intractable. Communication fabrics can be seen as a set of queues and flops interconnected by combinatorial logic. Based on this simple but powerful observation, we propose a novel method for liveness verification. Our method directly applies to Register Transfer Level designs. The essential aspects of our approach are (1) to abstract away from the details of queue implementations and (2) an efficient encoding of liveness properties in an SMT instance. Experimental results are promising. Designs with hundreds of queues can be analysed for liveness within minutes.},
Author = {Joosten, Sebastiaan Jozef Christiaan and Schmaltz, Julien},
Booktitle = {Design, Automation \& Test in Europe},
Organization = {European Design and Automation Association},
Pages = {113},
Title = {Scalable liveness verification for communication fabrics},
Year = {2014},
Month = {March},
Day = {24},
DOI = {10.7873/DATE.2014.126},
Local-Url = {DATE2014Scalable.pdf}}
@inproceedings{Joosten14,
Abstract = {This paper reports our initial experiments with using external ATP on some corpora built with the ACL2 system. This is intended to provide the first estimate about the usefulness of such external reasoning and AI systems for solving ACL2 problems.},
Author = {Joosten, Sebastiaan Jozef Christiaan and Kaliszyk, Cezary and Urban, Josef},
Booktitle = {ACL2 Workhop},
Pages = {77--85},
Title = {Initial Experiments with TPTP-style Automated Theorem Provers on ACL2 Problems},
Volume = {152},
Year = {2014},
Month = {Jul},
DOI = {10.4204/EPTCS.152.6},
Local-Url = {ACL22014Initial.pdf},
Slides = {SlidesJoosten14.pdf}}
@inproceedings{Joosten14b,
Abstract = {In modern chip architectures, the increase in parallelisation brings about highly complex on-chip communication fabrics. We present WickedXmas, a tool that facilitates the design and formal verification of such interconnects. The tool is based on the language xMAS, which is a high level design language for communication fabrics, originally proposed by Intel. The use of xMAS ensures that many common modelling errors such as unintended loss of data or dangling wires are prevented by construction. Therefore, the major challenge in verifying xMAS models is establishing deadlock freedom. WickedXmas can automatically detect deadlocks or prove their absence. If a deadlock is found, it is presented to the user for further analysis. Experimental evaluation on a range of interconnects shows good performance and scalability of WickedXmas in contrast to verification from scratch, or using existing model checking techniques. Using WickedXmas, a user can draw a communication fabric and formally verify it automatically.},
Author = {Joosten, Sebastiaan Jozef Christiaan and Verbeek, Freek and Schmaltz, Julien},
Booktitle = {International Workshop on Design and Implementation of Formal Tools and Systems (DIFTS)},
Title = {WickedXmas: Designing and Verifying on-chip Communication Fabrics},
Year = {2014},
Month = {Oct},
Day = {20},
Local-Url = {DIFTS2014WickedXmas.pdf}
}
@inproceedings{Joosten15,
Abstract = {Multi-core processors and Systems-on-Chips are composed of a large number of processing and memory elements interconnected by complex communication fabrics. These fabrics are large systems made of many queues and distributed control logic. Recent studies have demonstrated that high levels models of these networks are either tractable for verification or can provide key invariants to improve hardware model checkers. Formally verifying Register Transfer Level (RTL) designs of these networks is an important challenge, yet still open. This paper bridges the gap between high level models and RTL designs. We propose an algorithm that from a Verilog description automatically produces its corresponding micro-architectural model. We prove that the extracted model is transfer equivalent to the original RTL circuit. We illustrate our approach on a typical example of communication fabrics: a scoreboard with credit-flow control.},
Author = {Joosten, Sebastiaan Jozef Christiaan and Schmaltz, Julien},
Booktitle = {Design, Automation \& Test in Europe},
Organization = {EDA Consortium},
Pages = {1413--1418},
Title = {Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs},
Year = {2015},
Month = {Mar},
Local-Url = {DATE2015Automatic.pdf}}
@inproceedings{Joosten15a,
Abstract = {In the process of incorporating subtyping in relation algebra, an algorithm was found to derive the subtyping relation from the program to be checked. By using domain analysis rather than type inference, this algorithm offers an attractive visualization of the type derivation process. This visualization can be used as a graphical proof that the type system has assigned types correctly. An implementation is linked to in this paper, written in Haskell. The algorithm has been tried and tested in Ampersand, a language that uses relation algebra for the purpose of designing information systems.},
Author = {Joosten, Stef M M and Joosten, Sebastiaan Jozef Christiaan},
Booktitle = {International Conference on Relational and Algebraic Methods in Computer Science},
Organization = {Springer, Cham},
Pages = {225--240},
Title = {Type checking by domain analysis in {Ampersand}},
Year = {2015},
Month = {Sep},
Slides = {SlidesJoosten15a.pdf},
Note = {[Get source code that accompanies the paper](http://cs.ru.nl/~B.Joosten/ampTypes/)},
DOI = {10.1007/978-3-319-24704-5_14},
Local-Url = {RAMICS2015Type.pdf}}
@inproceedings{Wouda15,
Abstract = {We propose an algorithm for reachability analysis in micro-architectural models of communication fabrics. The main idea of our solution is to group transfers in what we call transfer islands. In an island, all transfers fire at the same time. To justify our abstraction, we give semantics of the initial models using a process algebra. We then prove that a transfer occurs in the transfer islands model if and only if the same transfer occurs in the process algebra semantics. We encode the abstract micro-architectural model together with a given state reachability property in the input format of nuXmv. Reachability is solved either using BDDs or IC3. Combined with inductive invariant generation techniques, our approach shows promising results.},
Author = {Wouda, Sanne and Joosten, Sebastiaan Jozef Christiaan and Schmaltz, Julien},
Booktitle = {Formal Methods and Models for Codesign (MEMOCODE), 2015 ACM/IEEE International Conference on},
Organization = {IEEE},
Pages = {198--207},
Title = {Process algebra semantics \& reachability analysis for micro-architectural models of communication fabrics},
Year = {2015},
Month = {Sep},
DOI = {10.1109/MEMCOD.2015.7340487},
Local-Url = {MEMOCODE2015Process.pdf}}
@phdthesis{joosten2016verification,
Abstract = {A communication fabric, or a Network on Chip (NoC), is a way to combine hardware components. For the final hardware to function correctly, it is critical that at least this NoC functions correctly. Some methods to prove the correctness of NoCs exist. An important property of correct NoCs, which turns out to be particularly difficult to prove, is that local deadlocks should not arise. We call NoCs live if they do not have such local deadlocks. Liveness proofs for networks that are large enough to be interesting in practice, used to exist only on an abstract level, or rely heavily on information from the abstract level.
To prove correctness of the concrete implementation of a NoC, we view the network as a set of queues an other state-holding elements, together with some combinational logic. This view lies very close to the actual hardware implementation. Queues and other state-holding elements are annotated through their interface. For this reason, we call this view on hardware the `interface level'.
The gate level implementation of a NoC design can be translated to combinational logic. At the gate level implementations, hardware designers make use of open wires and multi-directional gates. Where usual translations of gate level implementations are restricted to acyclic circuits with only binary gates, we show how to translate a richer class of gates to Boolean formulas. These Boolean formulas represent the gate level implementation of a NoC design.
In a proof about the correctness of a NoC, it can be important to know whether some queues can hold packets in a specific way. Linear one-step inductive invariants turn out to be a powerful tool to answer this question. Finding the right linear one-step inductive invariant used to require a high level description of the NoC. The essential property that is used describes when a packet of a certain type enters or leaves a queue: when a transfer occurs. By translating this property to a linear term, we can identify the linear invariants about the NoC. This property turns out to be available at the interface level. We describe how to translate this property to a linear term. As a consequence, we can automatically derive linear inductive invariants at the interface level.
To determine whether or not a NoC is live turns out to be very challenging. At the abstract level, there is a method that answer this question only partially: given a NoC, it can either prove that it is live, or it will present a situation which might be a reachable local deadlock. The latter case leaves the option open that the situation is not a reachable deadlock, in which case we still do not know whether or not the NoC is live. However, this methods has a good performance, and can determine liveness of NoCs of realistic sizes. We show that there is a similar algorithm at the interface level. Given a gate-level hardware description of a NoC, together with an interface specification of the queues, we formulate a Satisfiability Modulo Theory (SMT) problem that has an answer if the NoC has a reachable local deadlock. For many NoCs, the SMT problem turns out not to have an answer, which can be verified with standard SMT solvers. This proves that these NoCs are live, using only information that is available at the interface level.
We also reproduce an abstract-level description from the interface level. To do so, we give a procedure that constructs a tree of synchronising and arbitrating elements from the interface descriptions. Next, we orient the elements, deriving a graph in which all components are similar to the components in the xMAS language, a language for describing NoCs at an abstract level, proposed around 2010. For NoCs that were generated from xMAS, the resulting reproduced NoC is not necessarily equal to the original xMAS. Instead, we define a property called `transfer equivalence', and show that the resulting NoCs are transfer equivalent.
In addition to describing these novel techniques to analyse NoCs at the interface level, we have implemented the techniques as a proof of concept. Most of those implementations are now also available as part of a tool called Voi, which stands for `Verify on interfaces'. The tool Voi is implemented in Haskell, and we give some insight into its implementation. With this tool, we believe to have made a significant step towards the automated verification of gate-level descriptions of NoCs.},
Author = {Joosten, Sebastiaan Jozef Christiaan},
School = {Technische Universiteit Eindhoven},
Title = {Verification of Interconnects},
Year = {2016},
Month = {Feb},
Day = {24},
URL = {https://www.win.tue.nl/ipa/?event=verification-of-interconnects},
Local-Url = {PhdThesisJoosten.pdf}}
@inproceedings{Divason16,
Author = {Divas{\'o}n, Jose and Joosten, Sebastiaan Jozef Christiaan and Thiemann, Ren{\'e} and Yamada, Akihisa},
Booktitle = {Isabelle Workshop},
Title = {A Formalization of Berlekamp's Factorization Algorithm},
Year = {2016},
Month = {August},
Local-Url = {Isabelle2016Berlekamp.pdf}}
@article{Thiemann15,
Abstract = {Based on existing libraries for matrices, factorization of rational polynomials, and Sturm's theorem, we formalized algebraic numbers in Isabelle/HOL. Our development serves as an implementation for real and complex numbers, and it admits to compute roots and completely factorize real and complex polynomials, provided that all coefficients are rational numbers. Moreover, we provide two implementations to display algebraic numbers, an injective and expensive one, or a faster but approximative version.
To this end, we mechanized several results on resultants, which also required us to prove that polynomials over a unique factorization domain form again a unique factorization domain.},
Author = {Thiemann, Ren{\'e} and Yamada, Akihisa and Joosten, Sebastiaan Jozef Christiaan},
Journal = {Archive of Formal Proofs},
Title = {Algebraic Numbers in Isabelle/HOL},
Volume = {2015},
Year = {2015},
Month = {12},
Day = {22},
url = {https://www.isa-afp.org/entries/Algebraic_Numbers.html}}
@inproceedings{Joosten16,
Author = {Joosten, Sebastiaan Jozef Christiaan and Thiemann, Ren{\'e} and Yamada, Akihisa},
Booktitle = {15th International Workshop on Termination},
Editor = {Middeldorp, Aart and Thiemann, Ren{\'e}},
Title = {CeTA--Certifying Termination and Complexity Proofs in 2016},
Year = {2016},
Month = {Sep},
Local-Url = {CeTA-WST16.pdf}}
@inproceedings{Boerman18,
Abstract = {To increase the impact and capabilities of formal verification, it should be possible to apply different verification techniques on the same specification. However, this can only be achieved if verification tools agree on the syntax and underlying semantics of the specification language and unfortunately, in practice, this is often not the case.In this paper, we concentrate on one particular example, namely Java programs annotated with JML, and we present a case study in understanding differences in the treatment of these specifications. Concretely, we take a collection of JML-annotated programs, that we tried to reverify using KeY and OpenJML. This effort led to a list of syntactical and semantical differences in the JML support between KeY and OpenJML. We discuss these differences, and then derive some general principles on how to improve interoperability between verification tools, based on the experiences from this case study.},
Author = {Jan Boerman and Marieke Huisman and Joosten, Sebastiaan Jozef Christiaan},
Booktitle = {iFM 2018, LNCS},
Day = {5},
Editor = {Furia, {Carlo A.} and Kirsten Winter},
Language = {English},
Month = {9},
Pages = {1--17},
Title = {Reasoning About JML: Differences Between KeY and OpenJML},
Volume = {11023},
Year = {2018},
Local-Url = {IFM2018KeyOpenJML.pdf}}
@conference{Joosten18a,
Abstract = {Society nowadays relies heavily on software, which makes verifying the correctness of software crucially important. Various verification tools have been proposed for this purpose, each focusing on a limited set of tasks, as there are many different ways to build and reason about software. This paper discusses two case studies from the VerifyThis2018 verification competition, worked out using the VerCors verification toolset. Interestingly, these case studies are sequential, while VerCors specialises in reasoning about parallel and concurrent software. This paper elaborates on our experiences of using VerCors to verify sequential programs. The first case study involves specifying and verifying the behaviour of a gap buffer; a data-structure commonly used in text editors. The second case study involves verifying a combinatorial problem based on Project Euler problem #114. We find that VerCors is well capable of reasoning about sequential software, and that certain techniques to reason about concurrency can help to reason about sequential programs. However, the extra annotations required to reason about concurrency bring some specificational overhead.},
Author = {Joosten, Sebastiaan Jozef Christiaan and Wytse Oortwijn and Mohsen Safari and Marieke Huisman},
Day = {16},
Language = {English},
Month = {7},
Note = {20th Workshop on Formal Techniques for Java-like Programs Formal techniques : FTfJP 2018 with ECOOP and ISSTA, FTfJP 2018 ; Conference date: 16-07-2018 Through 21-07-2018},
Title = {An Exercise in Verifying Sequential Programs with VerCors},
Url = {https://conf.researchr.org/track/FTfJP-2018/FTfJP-2018-papers},
Year = {2018}}
@inbook{Divason18,
Abstract = {The LLL basis reduction algorithm was the first polynomial-time algorithm to compute a reduced basis of a given lattice, and hence also a short vector in the lattice. It thereby approximates an NP-hard problem where the approximation quality solely depends on the dimension of the lattice, but not the lattice itself. The algorithm has several applications in number theory, computer algebra and cryptography.In this paper, we develop the first mechanized soundness proof of the LLL algorithm using Isabelle/HOL. We additionally integrate one application of LLL, namely a verified factorization algorithm for univariate integer polynomials which runs in polynomial time.},
Author = {Jose Divas{\'o}n and Sebastiaan Jozef Christiaan Joosten and Ren{\'e} Thiemann and Akihisa Yamada},
Booktitle = {Interactive Theorem Proving},
Day = {4},
Doi = {10.1007/978-3-319-94821-8_10},
Editor = {Jeremy Avigad and Assia Mahboubi},
Isbn = {978-3-319-94820-1},
Language = {English},
Month = {7},
Note = {Open Access},
Pages = {160--177},
Publisher = {Springer},
Series = {Lecture Notes in Computer Science},
Title = {A Formalization of the LLL Basis Reduction Algorithm},
Year = {2018},
Bdsk-Url-1 = {https://doi.org/10.1007/978-3-319-94821-8_10}}
@inproceedings{Divason18d,
Author = {Jose Divas{\'o}n and Joosten, {Sebastiaan Jozef Christiaan} and Ren{\'e} Thiemann and Akihisa Yamada},
Booktitle = {16th International Workshop on Termination},
Editor = {Salvador Lucas},
Language = {English},
Month = {7},
Pages = {30--34},
Title = {A Perron-Frobenius Theorem for Jordan Blocks for Complexity Proving},
Year = {2018},
Local-URL = {WST2018PerronFrobenius.pdf}}
@article{Divason18c,
Abstract = {Short vectors in lattices and factors of integer polynomials are related. Each factor of an integer polynomial belongs to a certain lattice. When factoring polynomials, the condition that we are looking for an irreducible polynomial means that we must look for a small element in a lattice, which can be done by a basis reduction algorithm. In this development we formalize this connection and thereby one main application of the LLL basis reduction algorithm: an algorithm to factor square-free integer polynomials which runs in polynomial time. The work is based on our previous Berlekamp--Zassenhaus development, where the exponential reconstruction phase has been replaced by the polynomial-time basis reduction algorithm. Thanks to this formalization we found a serious flaw in a textbook.},
Author = {Jose Divas{\'o}n and Sebastiaan Jozef Christiaan Joosten and Ren{\'e} Thiemann and Akihisa Yamada},
Day = {6},
Issn = {2150-914x},
Journal = {Archive of Formal Proofs},
Language = {English},
Month = {2},
Note = {Formal proof development},
Publisher = {SourceForge},
Title = {A verified factorization algorithm for integer polynomials with polynomial complexity},
Year = {2018},
Url = {https://www.isa-afp.org/entries/LLL_Factorization.html}}
@article{Joosten18,
Abstract = {We give a procedure that can be used to automatically satisfy invariants of a certain shape. These invariants may be written with the operations intersection, composition and converse over binary relations, and equality over these operations. We call these invariants \tr{}s that we interpret over graphs. For questions stated through sets of these sentences, this paper gives a semi-decision procedure we call graph saturation. It decides entailment over these \tr{}s, inspired on graph rewriting. We prove correctness of the procedure. Moreover, we show the corresponding decision problem to be undecidable. This confirms a conjecture previously stated by the author.},
Author = {Joosten, {Sebastiaan Jozef Christiaan}},
Issn = {2352-2208},
Journal = {Journal of Logical and Algebraic Methods in Programming},
Keywords = {cs.LO, cs.DM, cs.PL},
Language = {English},
Month = {11},
Pages = {98--112},
Publisher = {Elsevier BV},
Title = {Finding models through graph saturation},
Volume = {100},
Year = {2018},
DOI = {10.1016/j.jlamp.2018.06.005},
Local-URL = {JLAMP2018Graph.pdf}}
@article{Divason18b,
Abstract = {The Lenstra-Lenstra-Lov{\'a}sz basis reduction algorithm, also known as LLL algorithm, is an algorithm to find a basis with short, nearly orthogonal vectors of an integer lattice. Thereby, it can also be seen as an approximation to solve the shortest vector problem (SVP), which is an NP-hard problem, where the approximation quality solely depends on the dimension of the lattice, but not the lattice itself. The algorithm also possesses many applications in diverse fields of computer science, from cryptanalysis to number theory, but it is specially well-known since it was used to implement the first polynomial-time algorithm to factor polynomials. In this work we present the first mechanized soundness proof of the LLL algorithm to compute short vectors in lattices. The formalization follows a textbook by von zur Gathen and Gerhard.},
Author = {Jose Divas{\'o}n and Sebastiaan Jozef Christiaan Joosten and Ren{\'e} Thiemann and Akihisa Yamada},
Issn = {2150-914x},
Journal = {Archive of Formal Proofs},
Language = {English},
Publisher = {SourceForge},
Title = {A verified LLL algorithm},
Volume = {2018},
Year = {2018},
Month = {2},
Day = {2},
Url = {https://www.isa-afp.org/entries/LLL_Basis_Reduction.html}}
@inproceedings{Divason17,
Abstract = {We formalize the Berlekamp--Zassenhaus algorithm for factoring square-free integer polynomials in Isabelle/HOL. We further adapt an existing formalization of Yun's square-free factorization algorithm to integer polynomials, and thus provide an efficient and certified factorization algorithm for arbitrary univariate polynomials. The algorithm first performs a factorization in the prime field GF(p) and then performs computations in the ring of integers modulo pk, where both p and k are determined at runtime. Since a natural modeling of these structures via dependent types is not possible in Isabelle/HOL, we formalize the whole algorithm using Isabelle's recent addition of local type definitions. Through experiments we verify that our algorithm factors polynomials of degree 100 within seconds.},
Address = {United States},
Author = {Jose Divas{\'o}n and Sebastiaan Jozef Christiaan Joosten and Ren{\'e} Thiemann and Akihisa Yamada},
Booktitle = {CPP 2017},
Doi = {10.1145/3018610.3018617},
Isbn = {978-1-4503-4705-1},
Language = {English},
Pages = {17--29},
Publisher = {Association for Computing Machinery},
Title = {A formalization of the Berlekamp-Zassenhaus factorization algorithm},
Year = {2017},
Month = {Jan},
Day = {16},
Note = {[Formalisation is online](https://www.isa-afp.org/entries/Berlekamp_Zassenhaus.html)},
Local-URL = {CPP17_Berlekamp_Zassenhaus.pdf}}
@inproceedings{Brockschmidt17,
Abstract = {Modern program analyzers translate imperative programs to an intermediate formal language like integer transition systems (ITSs), and then analyze properties of ITSs. Because of the high complexity of the task, a number of incorrect proofs are revealed annually in the Software Verification Competitions.In this paper, we establish the trustworthiness of termination and safety proofs for ITSs. To this end we extend our Isabelle/HOL formalization IsaFoR by formalizing several verification techniques for ITSs, such as invariant checking, ranking functions, etc. Consequently the extracted certifier CeTA can now (in)validate safety and termination proofs for ITSs. We also adapted the program analyzers T2 and AProVE to produce machinereadable proof certificates, and as a result, most termination proofs generated by these tools on a standard benchmark set are now certified.},
Author = {Marc Brockschmidt and Joosten, {Sebastiaan Jozef Christiaan} and Ren{\'e} Thiemann and Akihisa Yamada},
Booktitle = {Automated Deduction - CADE 26 International Conference on Automated Deduction},
Doi = {10.1007/978-3-319-63046-5_28},
Editor = {{de Moura}, Leonardo},
Isbn = {978-3-319-63045-8},
Language = {English},
Pages = {454--471},
Publisher = {Springer},
Series = {Lecture Notes in Artificial Intelligence},
Title = {Certifying safety and termination proofs for integer transition systems},
Year = {2017},
Month = {Aug},
Day = {11},
Local-URL = {CADE2017Certifying.pdf}}
@inproceedings{Divason18a,
Abstract = {Matrix interpretations are widely used in automated complexity analysis. Certifying such analyses boils down to determining the growth rate of $A^n$ for a fixed non-negative rational matrix $A$. A direct solution for this task involves the computation of all eigenvalues of $A$, which often leads to expensive algebraic number computations.
In this work we formalize the Perron--Frobenius theorem. We utilize the theorem to avoid most of the algebraic numbers needed for certifying complexity analysis, so that our new algorithm only needs the rational arithmetic when certifying complexity proofs that existing tools can find. To cover the theorem in its full extent, we establish a connection between two different Isabelle/HOL libraries on matrices, enabling an easy exchange of theorems between both libraries. This connection crucially relies on the transfer mechanism in combination with local type definitions, being a non-trivial case study for these Isabelle tools.},
Author = {Jose Divas{\'o}n and Sebastiaan Jozef Christiaan Joosten and Ondrej Kuncar and Ren{\'e} Thiemann and Akihisa Yamada},
Booktitle = {Proceedings of the 7th ACM SIGPLAN International Conference on Certified Programs and Proofs},
Doi = {10.1145/3167103},
Language = {English},
Pages = {2--13},
Title = {Efficient certification of complexity proofs: formalizing the Perron--Frobenius theorem (invited talk paper)},
Year = {2018},
Month = {Jan},
Local-Url={CPPDivason18a.pdf}
}
@inproceedings{Joosten17a,
Abstract = {We introduce the tool Amperspiegel, which uses triple graphs for parsing, printing and manipulating data. We show how to conveniently encode parsers, graph manipulation-rules, and printers using several relations. As such, parsers, rules and printers are all encoded as graphs themselves. This allows us to parse, manipulate and print these parsers, rules and printers within the system. A parser for a context free grammar is graph-encoded with only four relations. The graph manipulation-rules turn out to be especially helpful when parsing. The printers strongly correspond to the parsers, being described using only five relations. The combination of parsers, rules and printers allows us to extract Ampersand source code from ArchiMate XML documents. Amperspiegel was originally developed to aid in the development of Ampersand.},
Author = {Joosten, {Sebastiaan Jozef Christiaan}},
Booktitle = {Relational and algebraic methods in computer science},
Editor = {Peter H{\"o}fner and Damien Pous and Georg Struth},
Isbn = {978-3-319-57417-2},
Language = {English},
Pages = {159--176},
Publisher = {Springer},
Series = {Lecture Notes in Computer Science},
Title = {Parsing and Printing of and with Triples},
Year = {2017},
Month = {May},
Day = {16},
Slides = {SlidesJoosten17a.pdf},
Local-Url = {RAMICS2017Parsing.pdf}}
@article{Joosten17,
Abstract = {We formalize the theory of subresultants and the subresultant polynomial remainder sequence as described by Brown and Traub. As a result, we obtain efficient certified algorithms for computing the resultant and the greatest common divisor of polynomials.},
Author = {Sebastiaan Jozef Christiaan Joosten and Ren{\'e} Thiemann and Akihisa Yamada},
Day = {6},
Issn = {2150-914x},
Journal = {Archive of Formal Proofs},
Language = {English},
Month = {4},
Publisher = {SourceForge},
Title = {Subresultants},
Year = {2017},
Url = {https://www.isa-afp.org/entries/Subresultants.html}}