Effective Layered Verification of Interconnects
This was the topic of my PhD. My PhD Thesis is titled: Verification of Interconnects (Download the thesis or read the abstract here). Other publications relevant to this research include:
- Process algebra semantics & reachability analysis for micro-architectural models of communication fabrics
- Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs
- WickedXmas: Designing and Verifying on-chip Communication Fabrics
- Scalable liveness verification for communication fabrics
- Generation of inductive invariants from register transfer level designs of communication fabrics
- Formal deadlock verification for click circuits
- A macro for reusing abstract functions and theorems